----------------------------------------------------------------------------------
-- Company:        Johns Hopkins University
-- Engineer:       Kevin Green
--
-- Description:    This package includes some shared types and functions 
--  					 accross different modules. 
--
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;

package game_logic_pkg is

-- used types
type spot is (EMPTY, VALID, BLACK, WHITE);
type board is array (7 downto 0) of std_logic_vector(7 downto 0);
type g_board is array(7 downto 0, 7 downto 0) of spot;
	
-- function prototypes
function gen_flip_vector (col : std_logic_vector; in_board : board ) return std_logic_vector;
function gen_a1_h8_vec (col: std_logic_vector; row : std_logic_vector; in_board : board) return std_logic_vector;
function gen_a8_h1_vec (col: std_logic_vector; row : std_logic_vector; in_board : board) return std_logic_vector;

component KCPSM3
port (
      address       : out std_logic_vector( 9 downto 0);
      instruction   : in  std_logic_vector(17 downto 0);
      port_id       : out std_logic_vector( 7 downto 0);
      write_strobe  : out std_logic;
      out_port      : out std_logic_vector( 7 downto 0);
      read_strobe   : out std_logic;
      in_port       : in  std_logic_vector( 7 downto 0);
      interrupt     : in  std_logic;
      interrupt_ack : out std_logic;
      reset         : in  std_logic;
      clk           : in  std_logic
     );
end component;

-- picoblaze ram component
component gl_ctrl 
port (
      address     : in  std_logic_vector( 9 downto 0);
      instruction : out std_logic_vector(17 downto 0);
      clk         : in  std_logic
     );
end component;
	
end game_logic_pkg;

package body game_logic_pkg is
 
	-- the following functions perform some of the mapping between diagonal and vertical vectors
	-- this provides cleaner code in the other design modules
 
	function gen_a8_h1_vec (col: std_logic_vector; row : std_logic_vector; in_board : board) return std_logic_vector is
		variable u_temp : unsigned(2 downto 0);
	begin
		u_temp := ((7-unsigned(col))+unsigned(row));
		return in_board(to_integer(u_temp))(7) &
					in_board(to_integer(u_temp-1))(6) &
					in_board(to_integer(u_temp-2))(5) &
					in_board(to_integer(u_temp-3))(4) &
					in_board(to_integer(u_temp-4))(3) &
					in_board(to_integer(u_temp-5))(2) &
					in_board(to_integer(u_temp-6))(1) &
					in_board(to_integer(u_temp-7))(0);
		
	end function;
 
	function gen_a1_h8_vec (col: std_logic_vector; row : std_logic_vector; in_board : board) return std_logic_vector is
		variable u_temp : unsigned(2 downto 0);
	begin
		u_temp := (unsigned(row)-(7-unsigned(col)));
		return in_board(to_integer(u_temp))(7) &
					in_board(to_integer(u_temp+1))(6) &
					in_board(to_integer(u_temp+2))(5) &
					in_board(to_integer(u_temp+3))(4) &
					in_board(to_integer(u_temp+4))(3) &
					in_board(to_integer(u_temp+5))(2) &
					in_board(to_integer(u_temp+6))(1) &
					in_board(to_integer(u_temp+7))(0);
	end function;
 
	function gen_flip_vector (col : std_logic_vector; in_board : board ) return std_logic_vector is
		variable temp_vec : std_logic_vector(7 downto 0);
	begin
		temp_vec := in_board(7)(to_integer(unsigned(col))) & 
						in_board(6)(to_integer(unsigned(col))) & 
						in_board(5)(to_integer(unsigned(col))) & 
						in_board(4)(to_integer(unsigned(col))) & 
						in_board(3)(to_integer(unsigned(col))) & 
						in_board(2)(to_integer(unsigned(col))) & 
						in_board(1)(to_integer(unsigned(col))) & 
						in_board(0)(to_integer(unsigned(col)));

		return temp_vec;
	end function;
 
end game_logic_pkg;
